Staff Digital Design Engineer

Job Title: Staff Digital Design Engineer

Location: Leuven, Belgium

Job Type: Permanent

Salary: DOE

Role Overview

Design advanced digital building blocks for various applications, incl. but not limited to power management, low-power & low-voltage applications.

Key Responsibilities

• Micro-architecture specification development and design documentation
• RTL development using VHDL or Verilog/System Verilog, according to functional requirements and following design guidelines
• Lint, CDC, Synthesis, & Power Optimization
• Soft and hard IP identification, selection and integration
• Timing and power constraints development
• Collaboration with analog design team for mixed-signal designs
• Collaboration with verification team in verification plan development and debug
• Collaboration with physical design team to close the design on timing and power

Experience Required

• B.S. or M.S. degree in Electrical Engineering, microelectronics preferred.
• 4+ yrs' industry experience in RTL development
• Advanced knowledge of RTL design using VHDL or Verilog/System Verilog
• Knowledge of UVM Testbench development
• Strong communication and presentation skills in English

Desirable

• Knowledge of mixed signal concepts
• Hands-on experience with synthesis and/or place-and-route
• Able to work in a team
• Good problem solving skills and being able to implement solutions autonomously
• Understanding of Dutch language